SH7065 Datasheet, PDF (514/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
• Pins placed in high-impedance state (MMT 6-phase output pins)
The 12 MMT (motor management timer) pins PD26/D26/PWOB/RxD3,
PD25/D25/PVOB/TxD3, PD24/D24/PUOB/SCK3, PD22/D22/PWOA/SCK0,
PD21/D21/PVOA/IRQ7, PD20/D20/PUOA/IRQ6, PE23/IRQ7/PWOB, PE22/IRQ6/PVOB,
PE21/IRQ5/PUOB, PE19/IRQ3/PWOA, PE18/IRQ2/PVOA, and PE17/IRQ1/PUOA/SCK0
are placed in the high-impedance state.
Falling edge detection: When a translation from high-to low-level input occurs on a POE pin.
Low level detection: Figure 11.18 shows the low level detection operation. Low level sampling is
performed 16 times in succession using the sampling clock set in ICSR. The input is not accepted
if a high level is detected even once among these samples.
The timing of entry of the MMT’s 6-phase output pins into the high-impedance state from the
sampling clock is the same for falling edge detection and low level detection.
Pφ
Sampling clock
POE input
PUOA
8, 16, or
128 clocks
All samples low-level
[1]
[2]
At least one high-level _[1]
[2]
sample
High-impedance state
[3]
[16] Flag set (POE accepted)
[13] Flag not set
Note: The other MMT 6-phase output pins also go to the high-impedance state at the same timing.
Figure 11.18 Low Level Detection Operation
Exiting High-Impedance State
MMT 6-phase output pins that have entered the high-impedance state as the result of input level
detection are released from this state by restoring them to their initial states by means of a power-
on reset, or by clearing all the POE flags in ICSR (POE0F to POE3F: bits 12 to 15).
Rev. 5.00 Sep 11, 2006 page 492 of 916
REJ09B0332-0500