SH7065 Datasheet, PDF (204/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 6 Interrupt Controller (INTC)
6.2.4 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following modules:
• Direct memory access controller (DMAC)
• Watchdog timer (WDT)
• Bus state controller (BSC)
• Timer pulse unit (TPU)
• Serial communication interface (SCI)
• Compare match timer (CMT)
• Motor management timer (MMT)
• A/D converter (A/D)
• Port output enable (POE (I/O))
As a different vector number is assigned to each source, it is not necessary to determine the source
in the exception service routine. A priority level in the range 0 to 15 can be set for each module
with interrupt priority registers E to L (IPRE to IPRL). In on-chip peripheral module interrupt
exception handling, the interrupt mask bits (I3 to I0) in the status register (SR) are set to the
priority level of the accepted on-chip peripheral module interrupt.
6.2.5 Interrupt Exception Vectors and Priority Order
Tables 6.4 to 6.6 show interrupt sources, vector numbers, vector table addresses, and default
interrupt priorities.
Each interrupt source is assigned a different vector number and vector table address offset. The
vector table address is calculated from the vector number and vector table address offset. In
interrupt exception handling, the start address of the exception service routine is fetched from the
vector table entry indicated by this vector table address. For the method of calculating the vector
table address, see table 5.4, Exception Vector Table Address Calculation, in section 5, Exception
Handling.
In IRQ mode, an interrupt priority level of 0 to 15 can be assigned to the IRQ interrupts using
interrupt priority registers A and B (IPRA, IPRB).
In IRL mode, IRL interrupts IRL15 to IRL1 are assigned interrupt priority levels 15 to 1,
respectively. The vectors shown in tables 6.3 to 6.5 can be used for the vector numbers of IRQ and
IRL interrupts.
Rev. 5.00 Sep 11, 2006 page 182 of 916
REJ09B0332-0500