SH7065 Datasheet, PDF (282/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Wait State Control
Wait state insertion in normal space access can be controlled by means of WCR settings. If the
WCR wait specification bits corresponding to a particular area are not zero, a software wait is
inserted in accordance with that specification. For details, see section 8.2.3, Wait Control
Registers (WCR_0 to WCR_3).
The number of Tw cycles specified in WCR are inserted as wait cycles using the basic interface
wait timing shown in figure 8.9.
CKE*
A25–A0
CSn
WR
HHBS–LLBS
Read
RD
D31–D0
Write
WRHH–WRLL
D31–D0
BS
DACKn
T1
Tw
T2
Note: * When the setting CKE = CKIO is made in clock mode 0 to 3, 6, or 7, CKE is identical to CKIO
on the timing chart.
In clock modes 4 and 5, the phases of CKE and CKIO do not coincide, but the relative
relationship of the AC specifications is the same as in the other clock modes.
Figure 8.9 Wait State Timing for Normal Space Access
(One Software Wait State Inserted)
Rev. 5.00 Sep 11, 2006 page 260 of 916
REJ09B0332-0500