SH7065 Datasheet, PDF (344/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
9.2.8 Chain Transfer Count Registers 0 to 3 (CHNCNT0 to CHNCNT3)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Chain transfer count registers 0 to 3 (CHNCNT0 to CHNCNT3) are 32-bit readable/writable
registers that specify the chain transfer count when chain transfer is set.
The value of these registers is undefined after a power-on reset, and in hardware standby mode
and software standby mode. If chain transfer is not to be enabled, either initialize these registers to
0 or set bit 16 (TES) in CHCRn to 1 before enabling transfer.
9.2.9 DMA Operation Register (DMAOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4
— — — — RC3 RC2 RC1 RC0 — — — —
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0
R/W: — — — — R/W R/W R/W R/W R R R R
Note: The AE and NMIF bits can only be cleared to 0 after being read as 1.
3210
— AE NMIF DME
0000
R R/(W)R/(W) R/W
The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the
DMAC transfer mode.
DMAOR bits are initialized to 0 after a power-on reset, and in hardware standby mode and
software standby mode.
Bits 15 to 12—Reserved: These bits are always read as 0 and cannot be modified.
Rev. 5.00 Sep 11, 2006 page 322 of 916
REJ09B0332-0500