SH7065 Datasheet, PDF (534/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 13 Watchdog Timer
TCNT write
15
Address: H'FFFF 1000
H'5A
87
0
Write data
TCSR write
15
Address: H'FFFF 1000
H'A5
87
0
Write data
Figure 13.2 Writing to TCNT and TCSR
Writing to RSTCSR
To write to RSTCSR, a word transfer must be made to address H'FFFF1002. RSTCSR cannot be
written to with a byte transfer instruction.
Figure 13.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF
bit (bit 7) differs from that for writing to the RSTE bit (bit 6).
To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the
lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the
RSTE bit, the upper byte must contain H'5A and the lower byte must contain the write data. This
writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the WOVF bit.
Writing 0 to WOVF bit
15
Address: H'FFFF 1002
H'A5
87
0
Write data
Writing to RSTE bit
15
Address: H'FFFF 1002
H'5A
87
0
Write data
Figure 13.3 Writing to RSTCSR
Reading TCNT, TCSR, and RSTCSR
These registers are read in the same way as other registers. The read addresses are H'FFFF1000 for
TCSR, H'FFFF1001 for TCNT, and H'FFFF1003 for RSTCSR. Byte transfer instructions must be
used to read these registers.
Rev. 5.00 Sep 11, 2006 page 512 of 916
REJ09B0332-0500