SH7065 Datasheet, PDF (932/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Appendix D Restrictions and Caution on HD64F7065S (and HD64F7065A Lots Prior to “1D5”)
Appendix D Restrictions and Caution on HD64F7065S
(and HD64F7065A Lots Prior to “1D5”)
In addition to the Usage Notes given at the end of each section, the following restrictions and
caution also apply to the HD64F7065S. Items D.5 and D.6 apply to all HD64F7065S lots and also
to HD64F7065A lots prior to “TD5”. Items D.1 to D.4 apply only to all HD64F7065S lots.
D.1 BSC Restrictions
1. EDO DRAM burst operation is not supported when Mφ (the clock obtained after frequency
division of the master clock (CKM)) is faster than CKE (the external bus clock).
2. When wait cycle control is performed by means of the external WAIT pin, the following
restrictions apply only when an 8-bit-bus width is set.
• The access size for external 8-bit space must be byte or word.
• Use two word accesses to access 32-bit data in external 8-bit space.
3. If the master clock (CKM) frequency exceeds 30 MHz, the inter-cycle idle number
specification by bits IW2 to IW0 in the area control register (ACR) is invalid. The inter-cycle
idle number in this frequency band is an indeterminate number between 0 and 7 cycles. The
following automatically inserted idle cycles are valid.
• Two idle cycles when switching from a read cycle to a write cycle in the same space
• One idle cycle when switching from a read cycle to a read cycle in a different space
• Two idle cycles when switching from a read cycle or write cycle to a write cycle in a
different space
D.2 Restrictions in Case of Contention between DSP Instruction and
DMAC Transfer
In on-chip ROM high-speed mode, a bug may occur under the following conditions during
program execution in on-chip ROM.
1. Contention between MOVX instruction execution and on-chip XRAM access by the DMAC
2. Contention between MOVY instruction execution and on-chip YRAM access by the DMAC
This bug may result in an incorrect result of MOVX or MOVY instruction execution.
On-chip XRAM access/on-chip YRAM access here refers to cases where either the transfer source
or transfer destination is on-chip XRAM/on-chip YRAM. The DMAC transfer mode (cycle-
steal/burst) is irrelevant.
Rev. 5.00 Sep 11, 2006 page 910 of 916
REJ09B0332-0500