SH7065 Datasheet, PDF (485/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
Bit 0—Output Compare Flag M (TGFM): Status flag that indicates the occurrence of a compare
match between TCNT and the TPDR register.
Bit 0: TGFM
0
1
Description
[Clearing condition]
When 0 is written to TGFM after reading TGFM = 1
[Setting condition]
When TCNT = TGRM
(Initial value)
11.2.4 Timer Counter (TCNT)
The timer counter (TCNT) is a 16-bit counter.
TCNT is initialized to H'0000 by a power-on reset and in standby mode. It is not initialized in
module standby mode. Only 16-bit access can be used on TCNT; 8-bit access is not possible.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
11.2.5 Timer Buffer Registers (TBR)
The timer buffer registers (TBR) function as 16-bit buffer registers. The MMT has three TBR
registers. The TBR value is transferred to the TGR register at the timing set in the TMDR register
(except in the case of a write to the TBR’s free operation address, in which case the value is
transferred to the TGR register immediately).
The TBR registers are initialized to H'FFFF by a power-on reset and in standby mode. They are
not initialized in module standby mode. Only 16-bit access can be used on the TBR registers; 8-bit
access is not possible.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Sep 11, 2006 page 463 of 916
REJ09B0332-0500