SH7065 Datasheet, PDF (474/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation
takes precedence and the write to the buffer register is not performed.
Figure 10.54 shows the timing in this case.
Pφ
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T1 T2
Buffer register
address
N
TGR
M
N
Buffer register
M
Figure 10.54 Contention between Buffer Register Write and Input Capture
Rev. 5.00 Sep 11, 2006 page 452 of 916
REJ09B0332-0500