SH7065 Datasheet, PDF (533/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 13 Watchdog Timer
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) in watchdog timer mode. This bit is not set in interval timer mode.
Bit 7: WOVF
0
1
Description
No TCNT overflow in watchdog timer mode
TCNT overflow has occurred in watchdog timer mode
[Clearing condition]
Cleared by reading WOVF, then writing 0 to WOVF
(Initial value)
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is to be generated in the
SH7065 if TCNT overflows in watchdog timer mode.
Bit 6: RSTE
Description
0
Internal reset is not performed if TCNT overflows
(Initial value)
1
Internal reset is performed if TCNT overflows
Note: The modules in the SH7065 are not reset, but TCNT and TCSR within the WDT are reset.
Bit 5—Reserved: This bit is always read as 0 and should only be written with 0.
Bits 4 to 0—Reserved: These bits are always read as 1 and should only be written with 1.
13.2.4 Notes on Register Access
The method of writing to the watchdog timer’s timer counter (TCNT), timer control/status register
(TCSR), and reset control/status register (RSTCSR) differs from that for other registers to prevent
inadvertent overwriting. The procedures for writing to and reading these registers are given below.
Writing to TCNT and TCSR
A word transfer instruction must be used to write to TCNT and TCSR. They cannot be written to
with a byte transfer instruction.
Figure 13.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
Rev. 5.00 Sep 11, 2006 page 511 of 916
REJ09B0332-0500