SH7065 Datasheet, PDF (308/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.3.5 Multiplexed Address/Data I/O Interface
Basic Timing
A function is provided that performs multiplexed input/output of an address and data on pins D15
to D0 when the appropriate setting is made in bits TP1 and TP0 of the ACR1 registers for areas 1
to 3. This allows a peripheral LSI that requires address/data multiplexing to be connected to the
SH7065.
The bus width of multiplexed address/data I/O space is selected by the A14 bit. When A14 = 0,
the data bus width is 8 bits; the address is output at pins D15 to D0 and data is input/output at pins
D7 to D0. When A14 = 1, the address and data are both 16 bits, and address output and data
input/output is performed at pins D15 to D0.
In multiplexed address/data I/O space access, normal space type access is carried out after address
output has been performed for three cycles (fixed). The basic timing for multiplexed address/data
I/O space is shown in figure 8.31.
Rev. 5.00 Sep 11, 2006 page 286 of 916
REJ09B0332-0500