SH7065 Datasheet, PDF (215/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 6 Interrupt Controller (INTC)
Bits 7 to 0:
IRQ0F to IRQ7F
0
Detection Setting
Level detection
Edge detection
1
Level detection
Edge detection
Description
There is no IRQn interrupt request
[Clearing condition]
When IRQn input is high
An IRQn interrupt request has not been detected
[Clearing conditions]
• When 0 is written to IRQnF after reading IRQnF = 1
• When IRQn interrupt exception handling is executed
There is no IRQn interrupt request
[Setting condition]
When IRQn input is low
An IRQn interrupt request has been detected
[Setting condition]
When a falling edge occurs in IRQn input
The edge detection circuit operates at all times, even when level detection is set. Note, therefore,
that IRQnF may be set when a switch is made to edge detection after level detection operation. To
cancel an interrupt request (clear IRQnF) when using edge detection, read IRQnF and then write 0
to it. Figure 6.3 shows the interrupt control circuit.
IRQ pin
Level
detection
Edge
detection
ISR.IRQnF
IRQnS
(0: level,
1: edge)
SQ
Selection
CPU
interrupt
request
RESIRQn
R
(IRQn interrupt acceptance/IRQnF = 0 write after IRQnF = 1 read)
Figure 6.3 External Interrupt Process
Rev. 5.00 Sep 11, 2006 page 193 of 916
REJ09B0332-0500