SH7065 Datasheet, PDF (225/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 7 User Break Controller (UBC)
Section 7 User Break Controller (UBC)
7.1 Overview
The user break controller (UBC) provides functions that simplify program debugging. When break
conditions are set in the UBC, a user break interrupt is generated according to the conditions of the
bus cycle generated by the CPU or on-chip DMAC. This function makes it easy to design an
effective self-monitoring debugger, enabling programs to be debugged with the chip alone,
without using a large-scale in-circuit emulator.
7.1.1 Features
The UBC has the following features:
• The following break conditions can be set:
 Address (bit masking possible)
Internal address bus (CAB)/internal address bus (IAB)/X memory address bus (XAB)/Y
memory address bus (YAB)
 Bus master
CPU cycle/DMA cycle
 Bus cycle
Instruction fetch/data access
 Read/write
 Operand size
Byte/word/longword
• User break interrupt generation on occurrence of break condition
A user-written user break interrupt exception routine can be executed.
• When a user break is set for a CPU instruction fetch, the break is effected before execution of
the next instruction (post-execution break).
Rev. 5.00 Sep 11, 2006 page 203 of 916
REJ09B0332-0500