SH7065 Datasheet, PDF (96/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Table 2.25 System Control Instructions
Instruction
Instruction Code Operation
Execution
States T Bit
CLRMAC
0000000000101000 0 → MACH, MACL
1
—
CLRT
0000000000001000 0 → T
1
0
LDC Rm,SR
0100mmmm00001110 Rm → SR
1
LSB
LDC Rm,GBR
0100mmmm00011110 Rm → GBR
1
—
LDC Rm,VBR
0100mmmm00101110 Rm → VBR
1
—
LDC
Rm,MOD
0100mmmm01011110 Rm → MOD
1
—
LDC Rm,RE
0100mmmm01111110 Rm → RE
1
—
LDC Rm,RS
0100mmmm01101110 Rm → RS
1
—
LDC.L @Rm+,SR 0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm 3
LSB
LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm 3
—
LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm 3
—
LDC.L @Rm+,MOD 0100mmmm01010111 (Rm) → MOD, Rm + 4 → Rm 3
—
LDC.L @Rm+,RE 0100mmmm01110111 (Rm) → RE, Rm + 4 → Rm 3
—
LDC.L @Rm+,RS 0100mmmm01100111 (Rm) → RS, Rm + 4 → Rm 3
—
LDRE @(disp,PC) 10001110dddddddd disp × 2 + PC → RE
1
—
LDRS @(disp,PC) 10001100dddddddd disp × 2 + PC → RS
1
—
LDS
Rm,MACH 0100mmmm00001010 Rm → MACH
1
—
LDS
Rm,MACL 0100mmmm00011010 Rm → MACL
1
—
LDS
Rm,PR
0100mmmm00101010 Rm → PR
1
—
LDS
Rm,DSR
0100mmmm01101010 Rm → DSR
1
—
LDS
Rm,A0
0100mmmm01111010 Rm → A0
1
—
LDS
Rm,X0
0100mmmm10001010 Rm → X0
1
—
LDS
Rm,X1
0100mmmm10011010 Rm → X1
1
—
LDS
Rm,Y0
0100mmmm10101010 Rm → Y0
1
—
LDS
Rm,Y1
0100mmmm10111010 Rm → Y1
1
—
LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) → MACH, Rm + 4 → Rm 1
—
LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) → MACL, Rm + 4 → Rm 1
—
LDS.L @Rm+,PR 0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm 1
—
LDS.L @Rm+,DSR 0100mmmm01100110 (Rm) → DSR, Rm + 4 → Rm 1
—
Rev. 5.00 Sep 11, 2006 page 74 of 916
REJ09B0332-0500