SH7065 Datasheet, PDF (52/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
The DSR register is treated as a system register by CPU core instructions. The following
load/store instructions are used for data transfer to and from the DSR register.
STS DSR,Rn;
STS.L DSR,@-Rn;
LDS Rn,DSR;
LDS.L @Rn+,DSR;
The A0, X0, X1, Y0, and Y1 registers are also treated as system registers by CPU core
instructions. The following load/store instructions are used for data transfer to and from these
registers.
STS Dm,Rn;
STS.L Dm,@-Rn;
LDS Rn,Dm;
LDS.L @Rn+,Dm;
(Dm: A0, X0, X1, Y0, or Y1)
2.1.5 Notes on Guard Bits and Overflow Treatment
Data operations in the DSP unit are basically 32-bit operations, but these operations are always
executed with a 40-bit length including the 8-bit guard field. If the guard bit field does not match
the value of the MSB of the 32-bit field, the operation result is treated as overflow. In this case, the
N bit shows the correct status of the operation result regardless of whether or not overflow has
occurred. This also applies when the destination operand is a 32-bit register. The 8-bit guard bit
field is always assumed to present, and each status flag is updated.
If overflow occurs that prevents the result from being indicated correctly despite the use of the
guard bits, the N flag will not be able to show the correct status.
Rev. 5.00 Sep 11, 2006 page 30 of 916
REJ09B0332-0500