SH7065 Datasheet, PDF (562/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Bit 0—Receive Error (ER): Indicates that a framing error, parity error, or overrun error occurred
during reception.
Bit 0: ER
0
Description
Reception in progress, or reception has ended normally^*1
(Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When 0 is written to ER after reading ER = 1
1
A framing error, parity error, or overrun error occurred during reception
[Setting conditions]
• When the SCI checks whether the stop bit at the end of the receive data is
1 when reception ends, and the stop bit is 0^*2
• When, in reception, the number of 1-bits in the receive data plus the parity
bit does not match the parity setting (even or odd) specified by the O/E bit
in the serial mode register (SCSMR)
• When the next serial receive operation is completed while there are 16
receive data bytes in SCFRDR
Notes: 1. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is
cleared to 0. When a framing error or parity error occurs, the receive data is still
transferred to SCFRDR, and reception is then halted or continued according to the
setting of the EI bit. When an overrun error occurs, the receive data is not transferred to
SCFRDR and reception cannot be continued.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second bit is not
checked.
14.2.9 Bit Rate Register (SCBRR)
Bit: 7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The bit rate register (SCBRR) is an 8-bit register that sets the serial transmit/receive bit rate in
accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in the
serial mode register (SCSMR).
SCBRR can be read or written to by the CPU at all times.
Rev. 5.00 Sep 11, 2006 page 540 of 916
REJ09B0332-0500