SH7065 Datasheet, PDF (106/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Table 2.33 Correspondence between DSP Instruction Operands and Registers
Register
A0
A1
M0
M1
X0
X1
Y0
Y1
Legend:
Yes: Settable register
ALU/BPU Instructions
Sx
Sy
Dz
Du
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Multiply Instructions
Se
Sf
Dg
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
When writing parallel instructions, the B field instruction is written first, followed by the A field
instruction. A sample parallel processing program is shown in figure 2.13.
PADD A0, M0, A0 PMULS X0, Y0, M0
DCF PINC X1, A1
PCMP X1, M0
MOVX.W @R4+, X0
MOVX.W A0, @R5+R8
MOVX.W @R4
MOVY.W @R6+, Y0 [;]
MOVY.W @R7+, Y0 [;]
[NOPY] [;]
Figure 2.13 Sample Parallel Processing Program
Square brackets mean that the contents can be omitted. The no operation instructions NOPX and
NOPY can be omitted. A semicolon is the instruction line delimiter, but this can also be omitted. If
the semicolon delimiter is used, the area to the right of the semicolon can be used as a comment
field.
The DSR register status codes (DC, N, Z, V, and GT) are always updated by unconditional ALU
operation instructions and shift operation instructions. Conditional instructions do not update the
status codes even if the condition is satisfied. Multiply instructions, too, do not update the status
codes. The definition of the DC bit is determined by the specification of the CS bit in the DSR
register.
The DSP operation instructions are listed by type in table 2.34.
Rev. 5.00 Sep 11, 2006 page 84 of 916
REJ09B0332-0500