SH7065 Datasheet, PDF (781/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
Start
*1
Set SWE bit in FLMCR1
Wait 1 µs
n=1
Set EBR1
*3
Enable WDT
Set ESU bit in FLMCR1
Wait 100 µs
Set E bit in FLMCR1
Start of erase
Wait 10 ms
Clear E bit in FLMCR1
Erase halted
Wait 10 µs
Clear ESU bit in FLMCR1
Wait 10 µs
Disable WDT
Set EV bit in FLMCR1
Wait 6 µs
Set block start address to verify address
n←n+1
H'FF dummy write to verify address
Increment
address
No
Wait 2 µs
Read verify data
Verify data = all “1”?
Yes
Last address of block?
Yes
Clear EV bit in FLMCR1
*2
No
Clear EV bit in FLMCR1
Wait 4 µs
Wait 4 µs
No
*4
Erasing
of all erase blocks
completed?
Yes
Clear SWE bit in FLMCR1
No
n ≥ 100?
Yes
Clear SWE bit in FLMCR1
Wait 100 µs
Wait 100 µs
End of erase
Erase failure
Notes: 1. Preprogramming (setting erase block data to all “0”) is not necessary.
2. Verify data is read in 32-bit (longword) units.
3. Set only one bit in the erase block register (EBR). Two or more bits must not be set.
4. Erasing is performed in block units. For a multiple-block erase, the individual blocks must be erased sequentially.
Figure 19.14 Erase/Erase-Verify Flowchart (Single-Block Erase)
Rev. 5.00 Sep 11, 2006 page 759 of 916
REJ09B0332-0500