SH7065 Datasheet, PDF (326/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.5 Usage Notes
1. Even if a CAS assertion width of two cycles is set with the TCAS bit in DRAM control
register 2 (DCR2), the CAS assertion width will be one cycle in the second and subsequent
accesses when the access size exceeds the bus width (for example, accesses to addresses
4n+1/4n+2/4n+3 in the case of longword access to 8-bit-bus-width DRAM).
2. The following restrictions apply when using DRAM/EDO DRAM in RAS down mode.
• RAS down mode is not supported when Mφ (the clock obtained after frequency division of
the master clock (CKM)) is slower than CKE (the external bus clock).
• In the event of a row address miss, the CS signal for the next space to be accessed is
asserted for one cycle before external bus cycle generation.
• If the row address value in a CS4 space access is different from the previously accessed
CS5 space row address value, RAS1 is negated.
• In DMAC dual address mode, when the transfer source is CS4/5 space and the transfer
destination is CS space or on-chip register space, RAS1 is negated if the bit value
corresponding to the transfer destination row address is different from the transfer source
row address value.
• When the DMAC is activated in dual address mode immediately after a CS4/5 space access
by the CPU, and the transfer source is a different CS space or on-chip register space, RAS1
is negated if the bit value corresponding to the transfer source row address is different from
the row address value in the preceding CS4/5 space access by the CPU. This negation
occurs only in the case of a transfer immediately after DMAC activation. It does not occur
in the second and subsequent transfers when the DMAC is in burst mode.
• When the DMAC is activated with a different CS space access in single address mode
immediately after a CS4/5 space access by the CPU, RAS1 is negated if the bit value
corresponding to the different CS space row address is different from the row address value
in the preceding CS4/5 space access by the CPU. This negation occurs only in the case of a
transfer immediately after DMAC activation. It does not occur in the second and
subsequent transfers when the DMAC is in burst mode.
3. If a TAS instruction for the on-chip RAM space is executed while the bus is released, BACK is
first negated, then asserted again after execution is completed.
Rev. 5.00 Sep 11, 2006 page 304 of 916
REJ09B0332-0500