SH7065 Datasheet, PDF (420/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.2.4 Timer Interrupt Enable Registers (TIER)
Channel 0: TIER0
Channel 3: TIER3
Bit: 7
6
TTGE
—
Initial value:
0
1
R/W: R/W
—
5
4
3
2
1
0
—
TCIEV TGIED TGIEC TGIEB TGIEA
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit: 7
6
5
4
3
TTGE
—
TCIEU TCIEV
—
Initial value:
0
1
0
0
0
R/W: R/W
—
R/W
R/W
—
2
1
0
—
TGIEB TGIEA
0
0
0
—
R/W
R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset, and in hardware standby mode and software standby mode. They are
not initialized by the module standby function.
Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D
conversion start requests by TGRA input capture/compare match.
Bit 7: TTGE
0
1
Description
A/D conversion start request generation disabled
A/D conversion start request generation enabled
(Initial value)
Bit 6—Reserved: This bit is always read as 1 and cannot be modified.
Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by
the TCFU flag in TSR when TCFU is set to 1 in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Rev. 5.00 Sep 11, 2006 page 398 of 916
REJ09B0332-0500