SH7065 Datasheet, PDF (478/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the MMT. Pφ is obtained by division of CKP according to a
setting in the module clock division setting register.
TPBR TDDR
×2
TPDR
Comparators
TCNT
Magnitude comparators
Comparators
TDCNT0
PCO
PCI
Pφ
PUOA
PUOB
PVOA
PVOB
PWOA
PWOB
TBRU
TBRV
TBRW
TMDR
TCNT
TSR
Legend:
TGR: Timer general register
TBR: Timer buffer register
TDDR: Timer dead time data register
TPDR: Timer period data register
TPBR: Timer period buffer register
Td: Dead time
TMDR: Timer mode register
TCNR: Timer control register
TSR: Timer status register
TCNT: Timer counter
TDCNT: Timer dead time counter
Figure 11.1 Block Diagram of MMT
Rev. 5.00 Sep 11, 2006 page 456 of 916
REJ09B0332-0500