SH7065 Datasheet, PDF (296/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Burst Access
n addition to the normal DRAM access mode in which a row address is output in each data access,
a fast page mode is also provided for the case where consecutive accesses are made to the same
row. This mode allows fast access to data by outputting the row address only once, then changing
only the column address for each subsequent access. Normal access or burst access using fast page
mode can be selected by means of the BE bit in DCR3. The timing for burst access using fast page
mode is shown in figure 8.21.
Burst transfer is performed when the access width exceeds the bus width, or in single address
transfer in burst mode by the DMAC.
CKE
Tr Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2
A25–A0
Row Column
Column
Column
Column
CSn
RDWR
RASn
CASxxn
D31–D0
(read)
D31–D0
(write)
BS
DACKn
Figure 8.21 Basic Timing of DRAM Burst Access
Rev. 5.00 Sep 11, 2006 page 274 of 916
REJ09B0332-0500