SH7065 Datasheet, PDF (63/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Table 2.7 Delayed Branch Instructions
SH7065 CPU
BRA TRGET
ADD R1,R0
Description
ADD is executed before branch
to TRGET.
Example of Other CPU
ADD.W R1,R0
BRA TRGET
Multiply/Multiply and Accumulate Operations: A 16 × 16 → 32 multiply operation is executed
in 1 to 3 states, and a 16 × 16 + 64 → 64 multiply and accumulate operation in 2 to 3 states. A 32
× 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply and accumulate operation are
each executed in 2 to 4 states.
T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a
conditional branch is performed according to whether the result is True or False. Processing speed
has been improved by keeping the number of instructions that modify the T bit to a minimum.
Table 2.8 T Bit
SH7065 CPU
CMP/GE R1,R0
BT
TRGET0
BF
TRGET1
ADD
CMP/EQ
BT
#–1,R0
#0,R0
TRGET
Description
If R0 ≥ R1, the T bit is set.
A branch is made
to TRGET0 if R0 ≥ R1, or
to TRGET1 if R0 < R1.
The T bit is not set by ADD.
If R0 = 0, the T bit is set.
A branch is made if R0 = 0.
Example of Other CPU
CMP.W R1,R0
BGE TRGET0
BLT
TRGET1
SUB.W #1,R0
BEQ TRGET
Immediate Data: Byte immediate data is placed inside the instruction code. Word and longword
immediate data is not placed inside the instruction code, but in a table in memory. The table in
memory is referenced with an immediate data transfer instruction (MOV) using PC relative
addressing mode with displacement.
Rev. 5.00 Sep 11, 2006 page 41 of 916
REJ09B0332-0500