SH7065 Datasheet, PDF (321/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
On-Chip ROM
• In low-speed mode
All 2 cycles
• In high-speed mode
 Consecutive instruction fetch cycles
1 cycle (However, in a branch to address 8n+4 or 8n+6, consecutive instruction fetch
cycles immediately after the branch instruction fetch cycle comprise two cycles.)
 Branch instruction fetch cycle
2 to 3 cycles*
 Data read cycle
2 to 3 cycles*
Note: * The number of cycles depends on the state of the CPU pipeline, and buffering between
the internal 32-bit data bus (CDB) and the 64-bit internal data ROM bus.
Figures 8.36 to 8.43 show the CPU pipeline state and the number of on-chip ROM
access cycles when no on-chip ROM data read cycles are generated.
Address
Pipeline state
8n
8n + 2
8n + 4
8n + 6
8n + 8
8n + 10
8n + 12
8n + 14
<IF ID
IF
EX
ID EX
— ID EX
ID EX
IF — — ID EX
ID EX
IF — — ID EX
ID EX
Access
fetch fetch fetch nop fetch nop fetch nop fetch nop
Number ^{In low-speed mode 2}
2
2
1
2
1
21
21
of cycles _{In high-speed mode 2, 3 1}
1
1
1
1
11
11
Figure 8.36 Consecutive Execution of 16-Bit Instructions
(In Case of Branch to Address 8n)
Rev. 5.00 Sep 11, 2006 page 299 of 916
REJ09B0332-0500