SH7065 Datasheet, PDF (33/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 1 Overview
Type
Symbol
System control RES
I/O
Input
WDTOVF Output
BREQ
Input
BACK
Output
HSTBY
Input
Operating
MD0–MD5 Input
mode control
FWE
Input
Interrupts
NMI
Input
IRQ0–IRQ7 Input
IRQOUT Output
Address bus
Data bus
Bus control
A0–A25
D0–D31
CS0–CS5
Output
I/O
Output
RD
Output
RDWR
WRLL
Output
Output
WRLH
Output
Name
Power-on
reset
Watchdog
timer overflow
Bus request
Bus request
acknowledge
Hardware
standby
Mode setting
Flash write
enable
Nonmaskable
interrupt
Interrupt
request 0 to 7
Interrupt
request output
Address bus
Data bus
Chip select
0 to 5
Read
Read/write
LL write
LH write
Function
Executes a power-on reset when driven
low.
WDT overflow output signal
Driven low when an external device
requests release of the bus.
Indicates that the bus has been granted
to an external device. The device that
output the BREQ signal recognizes that
the bus has been acquired when it
receives the BACK signal.
Hardware standby input pin. Drive high
when not used.
These pins determine the operating
mode. Do not change the input values
during operation.
On-chip flash memory program/erase
hardware protection pin.
Nonmaskable interrupt request pin.
Acceptance at the rising edge or falling
edge can be selected.
Maskable interrupt request pins. Level
input or edge input can be selected.
Indicates that an interrupt request has
been generated. Enables interrupt
generation to be recognized in the bus-
released state.
Address output pins.
32-bit bidirectional data bus.
Chip select signals for external memory
or devices.
Indicates reading from an external
device.
Used as the DRAM write directive signal.
Indicates writing of bits 7 to 0 of external
data.
Indicates writing of bits 15 to 8 of
external data.
Rev. 5.00 Sep 11, 2006 page 11 of 916
REJ09B0332-0500