SH7065 Datasheet, PDF (771/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
19.7.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared, then the PSU bit is cleared at least 5 µs later). After the elapse of 5 µs or
more, the watchdog timer is cleared, and the operating mode is switched to program-verify mode
by setting the PV bit in FLMCR1. In program-verify mode, a dummy write of H'FF data should be
made to the addresses to be read. The dummy write should be executed after the elapse of 4 µs or
more. When the flash memory is read in this state (verify data is read in 32-bit units), the data at
the latched address is read. Wait at least 2 µs after the dummy write before performing this read
operation. Next, the originally written data is compared with the verify data, and reprogram data is
computed (see figure 19.13) and transferred to RAM. After 128 bytes of data have been verified,
exit program-verify mode, wait for at least 2 µs, then clear the SWE bit in FLMCR1. If
reprogramming is necessary, set program mode again, and repeat the program/program-verify
sequence as before. However, ensure that the program/program-verify sequence is not repeated
more than 1000 times on the same bits.
Rev. 5.00 Sep 11, 2006 page 749 of 916
REJ09B0332-0500