SH7065 Datasheet, PDF(934/941 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

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SH7065 Datasheet, PDF (934/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

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Appendix D Restrictions and Caution on HD64F7065S (and HD64F7065A Lots Prior to â1D5â)

D.6 Restrictions about Changing the Saturation Operation Mode during

the Execution of Multiply/Multiply and Accumulate, or DSP

Instructions

When instruction execution is stalled by the occurrence of multiplier contention between

Multiply/Multiply and Accumulate instructions, or register contention by the continuous execution

of DSP instructions, pay attention to the following:

If the S bit (saturation operation bit) of SR (status register) is changed directly after the execution

of Multiply/Multiply and Accumulate or DSP instructions, the sequences of these instructions can

be reversed. AS a result, an instruction that should be executed before the change of the S bit can

be executed after the change of the S bit, and the result of the instruction may be wrong.

Instructions that can be affected by the change of the S bit

â¢ Multiply and Accumulate instructions: MAC.W, MAC.L

â¢ DSP instructions: ALU Arithmetic operation instructions, Fixed-point multiply instruction,

Arithmetic shift operation instructions

Examples for the wrong operation cases are shown below:

1. In case of Multiply/Multiply and Accumulate instructions

(a) DMULU.L R4,R10

(b) MAC.L @R5+,@R5+

(c) LDC

R0,SR

MUL.L, DMULS.L, DMULU.L, and MAC.L can be

applied.

MAC.W and MAC.L can be applied. Instruction execution

is stalled by the occurrence of multiplier contention.

Saturation operation mode is changed.

Multiplier contention is occurred between (a) DMULU.L instruction and (b) MAC.L

instruction, and the execution of (b) MAC.L instruction is stalled. The changing of the S bit by

(c) instruction is executed in the CPU before the execution of (b) MAC.L instruction due to the

pipeline control. As a result, the sequence of (b) and (c) instructions is reversed, and the result

of the MAC.L instruction becomes to be wrong.

Rev. 5.00 Sep 11, 2006 page 912 of 916

REJ09B0332-0500

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