SH7065 Datasheet, PDF (337/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Bit 23—Reserved: This bit is always read as 0 and cannot be modified.
Bit 22—FIFO Select (FIFOS): Selects the FIFO to be used for DREQ level detection. This bit is
invalid when DREQ falling edge detection is used.
Bit 22: FIFOS
0
1
Description
1-stage FIFO is used for DREQ level detection
16-stage FIFO is used for DREQ level detection
(Initial value)
Bits 21 and 20—Reserved: These bits are always read as 0 and cannot be modified.
Bit 19—Next Destination Address Register Enable (NDARE): Selects whether or not the next
destination address register value is to be transferred to the destination address register to update
the destination address during chain transfer.
Bit 19: NDARE
0
1
Description
In chain transfer, next destination address register value is not copied to
destination address register
(Initial value)
In chain transfer, next destination address register value is copied to
destination address register
Bit 18—Next Source Address Register Enable (NSARE): Selects whether or not the next
source address register value is to be transferred to the source address register to update the source
address during chain transfer.
Bit 18: NSARE
0
1
Description
In chain transfer, next source address register value is not copied to source
address register
(Initial value)
In chain transfer, next source address register value is copied to source
address register
Bit 17—Flag Clear Timing Select (FCS): When a transfer request by an on-chip module is
accepted, the DMAC outputs a signal to clear the transfer request flag of the on-chip module that
made the transfer request. This bit selects whether this output is to be performed in the bus cycle
in which the transfer count register (DMATCRn) value becomes 0, or in every bus cycle. When
this bit is set to 1, the edge detection setting should be made in bit 6 (DREQ Select: DS).
Rev. 5.00 Sep 11, 2006 page 315 of 916
REJ09B0332-0500