SH7065 Datasheet, PDF (93/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Instruction
Instruction Code
Operation
Execution
States T Bit
SUBC Rm,Rn
0011nnnnmmmm1010 Rn – Rm – T → Rn,
1
borrow → T
Borrow
SUBV Rm,Rn
0011nnnnmmmm1011 Rn – Rm → Rn,
1
underflow → T
Underflow
Note: * The normal number of execution states is shown. The number in parentheses is the
number of execution cycles in the case of contention with preceding or following
instructions.
Table 2.22 Logic Operation Instructions
Instruction
Instruction Code Operation
AND Rm,Rn
0010nnnnmmmm1001 Rn & Rm → Rn
AND #imm,R0
11001001iiiiiiii R0 & imm → R0
AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm →
(R0 + GBR)
NOT Rm,Rn
0110nnnnmmmm0111 ~Rm → Rn
OR Rm,Rn
0010nnnnmmmm1011 Rn | Rm → Rn
OR #imm,R0
11001011iiiiiiii R0 | imm → R0
OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm →
(R0 + GBR)
TAS.B @Rn
0100nnnn00011011 When (Rn) = 0, 1 → T,
1 → MSB of (Rn)
TST Rm,Rn
0010nnnnmmmm1000 Rn & Rm;
when result = 0, 1 → T
TST #imm,R0
11001000iiiiiiii R0 & imm;
when result = 0, 1 → T
TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm;
when result = 0, 1 → T
XOR Rm,Rn
0010nnnnmmmm1010 Rn ^ Rm → Rn
XOR #imm,R0
11001010iiiiiiii R0 ^ imm → R0
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm →
(R0 + GBR)
Execution
States T Bit
1
—
1
—
3
—
1
—
1
—
1
—
3
—
4
Test
result
1
Test
result
1
Test
result
3
Test
result
1
—
1
—
3
—
Rev. 5.00 Sep 11, 2006 page 71 of 916
REJ09B0332-0500