SH7065 Datasheet, PDF (217/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 6 Interrupt Controller (INTC)
Program execution state
Interrupt
No
generated?
Yes
No
NMI?
Yes
User break?
No
Yes
Level 15
No
interrupt?
No
Yes
Yes
I3 to I0 =
level 14 or lower?
Level 1
No
interrupt?
Yes
*1
IRQOUT = low
Save SR to stack
No
Yes
I3 to I0 =
level 0?
No
Save PC to stack
Copy interrupt level
to I3 to I0
Read vector number
IRQOUT = high ^*2
Read exception
vector table
Branch to exception
service routine
Notes: I3 to I0: Interrupt mask bits in the CPU’s status register (SR).
1. IRQOUT is the same signal as the interrupt request signal sent to the CPU (see figure 6.1), and so is output in the
event of an interrupt request with a higher priority level than that set in bits I3 to I0 in SR.
2. If the accepted interrupt is edge-detected, IRQOUT goes high at the point at which the instruction about to be
executed by the CPU is replaced by interrupt exception handling (before SR is saved to the stack). If the interrupt
controller is accepting another interrupt with a higher priority level and an interrupt request is being output to the
CPU, the IRQOUT pin remains low.
Figure 6.4 Interrupt Operation Flowchart
Rev. 5.00 Sep 11, 2006 page 195 of 916
REJ09B0332-0500