SH7065 Datasheet, PDF (789/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
FLER bit setting conditions are as follows:
1. When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
2. Immediately after the start of exception handling (excluding a reset and hardware standby
mode) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the bus is released during programming/erasing
Error protection is released only by a reset or in hardware standby mode.
Figure 19.15 shows the flash memory state transition diagram.
Program mode
Erase mode
RD VF PR ER FLER = 0
RES = 0 or HSTBY = 1
Reset or standby
(hardware protection)
RD VF PR ER FLER = 0
Error
occurrence
Error occurrence
(software standby)
RES = 0 or
HSTBY = 1
RES = 0 or
HSTBY = 1
FLMCR1, EBR1,
EBR2 initialization
state
Error protection mode
RD VF PR ER FLER = 1
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
Software
standby mode
Software standby
mode release
Error protection mode
(standby)
RD VF PR ER FLER = 1
FLMCR1, EBR1, EBR2
initialization state
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Figure 19.15 Flash Memory State Transitions
Rev. 5.00 Sep 11, 2006 page 767 of 916
REJ09B0332-0500