SH7065 Datasheet, PDF (837/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 22 Electrical Characteristics
22.3.4 Direct Memory Access Controller Timing
Table 22.7 Direct Memory Access Controller Timing
Conditions: V_CC = PLLV_CC = 3.0 to 3.6 V, AV_CC = 3.0 to 3.6 V, AV_CC = V_CC ±10%,
V_SS = PLLV_SS = PV_SS = AV_SS = 0 V, Ta = –20 to +75°C
Item
DREQ0, DREQ1 setup time
DREQ0, DREQ1 hold time
DREQ0, DREQ1 pulse time
DRAK output delay time
TEND output delay time
Symbol Min
tDRQS
16
tDRQH
16
tDRQW
2.5
tDRAKD
—
tTED

Max
Unit Figure
—
ns
Figure 22.21,
Figure 22.23
—
ns
Figure 22.21
—
tcyc Figure 22.22
16
ns
Figure 22.23,
Figure 22.24
16
ns
Figure 22.25
CKE
DREQ0/DREQ1
level
t_DRQS
DREQ0/DREQ1
edge
t_DRQS
t_DRQH
DREQ0/DREQ1
level clearing
(when using
16-stage FIFO)
t_DRQS
Figure 22.21 DREQ0 and DREQ1 Input Timing (1)
Rev. 5.00 Sep 11, 2006 page 815 of 916
REJ09B0332-0500