SH7065 Datasheet, PDF (87/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Type
Branch
instructions
Kinds of
Instruction
9
Op Code
BF
BT
System control 14
instructions
Total: 65
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
CLRMAC
CLRT
LDC
LDRE
LDRS
LDS
NOP
RTE
SETRC
SETT
SLEEP
STC
STS
TRAPA
Section 2 CPU
Function
Number of
Instructions
Condition branch, delayed
11
conditional branch
(branches if T = 0)
Condition branch, delayed
conditional branch
(branches if T = 1)
Unconditional branch
Unconditional branch
Branch to subroutine procedure
Branch to subroutine procedure
Unconditional branch
Branch to subroutine procedure
Return from subroutine procedure
MAC register clear
71
T bit clear
Load into control register
Load into repeat end register
Load into repeat start register
Load into system register
No operation
Return from exception handling
Repeat count setting
T bit setting
Transition to power-down mode
Store from control register
Store from system register
Trap exception handling
Total: 182
Rev. 5.00 Sep 11, 2006 page 65 of 916
REJ09B0332-0500