SH7065 Datasheet, PDF (615/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Table 14.12 Bits ICK3 to ICK0 and Operating Frequencies in IrDA mode(When PSEL = 1)
Operating Frequency
Pφ (MHz)
2
3
5
6
8
10
12
14
16
18
20
21
22
23
24
25
26
27
28
ICK3
0
1
Setting of Bits ICK3 to ICK0
ICK2
ICK1
0
0
1
1
0
1
0
0
1
1
0
1
ICK0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
0
1
14.4 SCI Interrupt Sources and the DMAC
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-FIFO-data-full interrupt (RXI) request, and transmit-FIFO-data-empty
interrupt (TXI) request.
Table 14.13 shows the interrupt sources and their relative priorities. Individual interrupt sources
can be enabled or disabled with the TIE, RIE, and TEIE bits in SCSCR. Each kind of interrupt
request is sent to the interrupt controller independently.
When the TDFE flag is set to 1 in the serial status register (SC1SSR), a TXI interrupt is requested.
A TXI interrupt request can activate the on-chip DMAC to perform data transfer. The TDFE bit is
Rev. 5.00 Sep 11, 2006 page 593 of 916
REJ09B0332-0500