SH7065 Datasheet, PDF (479/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
11.1.3 Pin Configuration
Table 11.1 shows the pin configuration of the MMT.
Table 11.1 MMT Pins
Pin Name
Counter clear input
PWM period output
Signal Name
PCI
PCO
I/O
Input
Output
PWMU phase output A
PWMU phase output B
PWMV phase output A
PWMV phase output B
PWMW phase output A
PWMW phase output B
PUOA
PUOB
PVOA
PVOB
PWOA
PWOB
Output
Output
Output
Output
Output
Output
Function
Counter clear signal input
Toggle output synchronized with PWM
period
PWMU phase output (positive phase)
PWMU phase output (negative phase)
PWMV phase output (positive phase)
PWMV phase output (negative phase)
PWMW phase output (positive phase)
PWMW phase output (negative phase)
11.1.4 Register Configuration
Table 11.2 summarizes the MMT registers.
Table 11.2 MMT Registers
Name
Timer mode register
Timer control register
Timer status register
Timer counter
Timer buffer register U
Abbre-
viation
TMDR
TCNR
TSR
TCNT
TBRU
Timer buffer register V
TBRV
Timer buffer register W
TBRW
Timer general register UU
TGRUU
R/W
R/W
R/W
R/(W)
R/W
R/W
Initial
Value
H'00
H'00
H'80
H'0000
H'FFFF
R/W H'FFFF
R/W H'FFFF
R/W H'FFFF
Address
H'FFFF 0480
H'FFFF 0482
H'FFFF 0484
H'FFFF 0486
H'FFFF 0490,
H'FFFF 049C^*
H'FFFF 04A0,
H'FFFF 04AC^*
H'FFFF 04B0,
H'FFFF 04BC^*
H'FFFF 0492
Access Size
8, 16, 32
8, 16, 32
8, 16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
Rev. 5.00 Sep 11, 2006 page 457 of 916
REJ09B0332-0500