SH7065 Datasheet, PDF (267/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Bit 3:
TRAS2
0
1
Bit 2:
TRAS1
0
1
0
1
Bit 1:
TRAS0
0
1
0
1
0
1
0
1
Description
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
Section 8 Bus State Controller (BSC)
(Initial value)
Bit 0—Reserved: This bit is always read as 0 and should only be written with 0.
8.2.8 Refresh Timer Counter (RTCNT)
The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by
the input clock selected by bits CKS2 to CKS0 in the RTCSR register. When the RTCNT counter
value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the
RTCNT counter is cleared.
RTCNT bits 15 to 8 are reserved; they are always read as 0 and should only be written with 0.
RTCNT is initialized to H'00 by a power-on reset. In standby mode, RTCNT is not initialized, and
retains its contents.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
RTCNT7 RTCNT6 RTCNT5 RTCNT4 RTCNT3 RTCNT2 RTCNT1 RTCNT0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Sep 11, 2006 page 245 of 916
REJ09B0332-0500