SH7065 Datasheet, PDF (338/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Bit 17: FCS
Description
0
When an on-chip module is the transfer request source, the DMAC outputs the
flag clearing signal in the bus cycle in which the transfer count register
(DMATCRn) value becomes 0
(Initial value)
1
When an on-chip module is the transfer request source, the DMAC outputs the
flag clearing signal in every last bus cycle
Note: When DREQ is edge-detected, FCS can be used to select the edge clearing timing.
Bit 16—Transfer End Setting Select (TES): Specifies whether the transfer end bit (TE) is to be
set at the end of all the chain transfers specified in the chain count register (CHNCNT), or at the
end of the number of data transfers specified by DMATCRn.
This bit is valid regardless of the setting of bit 11 (Chain Transfer Enable: CHNE). Therefore,
when not performing chain transfer, either set this bit to 1 or else set a value of 0 in the CHNCNT.
When bit 2 (Interrupt Enable: IE) is set to 1, a transfer end interrupt (DEI) is requested when the
transfer end bit is set at the timing specified by this bit.
Bit 16: TES
Description
0
Transfer end bit (TE) is set to 1 when CHNCNTn = 0 and DMATCRn = 0
(Initial value)
1
Transfer end bit (TE) is set to 1 when DMATCRn = 0
Note: With auto-request, this bit is invalid and an interrupt is requested when DMATCRn = 0.
When auto-request is selected, TES = 1 operation is used.
Bits 15 and 14—Destination Address Modes 1 and 0 (DM1, DM0): These bits specify
incrementing/decrementing of the DMA transfer destination address. The specification of these
bits is ignored when data is transferred from address space to an external device in single address
mode.
Bit 15: DM1
0
1
Bit 14: DM0
0
1
0
1
Description
Destination address fixed
(Initial value)
Destination address incremented (+1 in 8-bit transfer, +2
in 16-bit transfer, +4 in 32-bit transfer)
Destination address decremented (–1 in 8-bit transfer, –2
in 16-bit transfer, –4 in 32-bit transfer)
(Use prohibited)
Rev. 5.00 Sep 11, 2006 page 316 of 916
REJ09B0332-0500