SH7065 Datasheet, PDF (520/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 12 Compare Match Timer (CMT)
Bits 5 to 2—Reserved: These bits are always read as 0 and cannot be modified.
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock to be input to
CMCNT from four internal clocks obtained by frequency division of Pφ. When the STR bit is set
to 1 in CMSTR, CMCNT starts counting up on the clock selected by CKS1 and CKS0.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
Pφ/8
Pφ/32
Pφ/128
Pφ/512
(Initial value)
12.2.3 Compare Match Counters 0 and 1 (CMCNT0, CMCNT1)
The compare match counters (CMCNT0, CMCNT1) are 16-bit registers used as up-counters to
generate interrupt requests.
When an internal clock is selected with bits CKS1 and CKS0 in CMCSR, CMCNT starts counting
up on that clock. When the CMCNT value matches the value in the compare match constant
register (CMCOR), CMCNT is cleared to H'0000 and the CMF flag is set to 1 in CMCSR. If the
setting of the CMIE bit in CMCSR is 1 at this time, a compare match interrupt (CMI0 or CMI1) is
requested.
The CMCNT registers are initialized by a power-on reset, and in hardware standby mode and
software standby mode.
Bit: 15
14
13
12
11
10
9
8
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Sep 11, 2006 page 498 of 916
REJ09B0332-0500