SH7065 Datasheet, PDF (182/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
4.14.3 Exit from Module Clock Division Function
The module clock division function is exited by setting the MCLK bits.
4.14.4 Notes on Use of Module Clock Division Function
1. The module clock division ratio is changed by writing the required value in the MCLK bits in
the MCLKCR register.
The write to MCLKCR must be executed by a program in on-chip RAM or on-chip ROM.
Also note that the DMAC must not be used to access MCLKCR.
If the frequency ratio of Mφ (the clock resulting from master clock (CKM) division) to CKE
(the external bus clock) changes as a result of the frequency change, after the change the
MCLKCR5 register must be read before
• an external space access, or
• a transition to sleep mode.
(The MCLKCR5 register value read at this time will be undefined.)
When changing Pφ (the clock resulting from peripheral clock (CKP) division), after the change
a register in the module corresponding to the changed Pφ must be read before
• accessing a register in the module corresponding to the changed Pφ,
• entering the module standby state for the module corresponding to the changed Pφ,
• changing the changed Pφ again, or
• entering software standby mode.
(The register value read at this time will be undefined.)
2. Ensure that CKM, CKP, CKE, and Mφ and Pφ supplied to the modules, do not exceed their
maximum frequency while the setting is being made.
3. Immediately after the value of the MCLK bits is changed, the module corresponding to the
changed Mφ or Pφ will temporarily enter the module standby state. Therefore, when an MCLK
bit value corresponding to the SCI or A/D converter is changed, the SCI or A/D converter
registers are initialized. However, there is no temporary transition to the module standby state
if the same value is written to the MCLK bits.
4. Do not set a combination that gives a division ratio of Mφ:CKE = 1/8:1/4 (taking the clock
input to dividers 1 to 4 in the CPG as 1); that is, a combination giving a CPG division setting
of CKM:CKE = 1:1/4, and a module clock division setting of CKM:Mφ = 1:1/8.
Rev. 5.00 Sep 11, 2006 page 160 of 916
REJ09B0332-0500