SH7065 Datasheet, PDF (152/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
Notes: The lower and upper limits of the clock input frequency range are determined by the
following conditions:
1. Lower-limit frequency
The output frequency of each PLL before division must be at least 10 MHz. The specific
clock input frequency lower limits are as follows: 2.5 MHz in clock modes 2, 3, 4, and 5
(as the PLL2 multiplication factor is ×4), 5 MHz in clock modes 0 and 1 (as the PLL2
multiplication factor is ×2), 5 MHz also in clock mode 6 (as the PLL1 multiplication factor
is ×2), and 10 MHz in clock mode 7 (as the PLL1 multiplication factor is ×1).
2. Upper-limit frequency
(1) Clock upper limits after division according to FRQCR register setting
CKM ≤ 60 MHz, CKP ≤ 60 MHz, CKE ≤ 30 MHz
(2) Clock upper limits after division according to MCLKCR1-5 register setting
Mφ ≤ 60 MHz, Pφ ≤ 30 MHz
The frequency that satisfies both (1) and (2) above is the clock input frequency upper
limit.
Rev. 5.00 Sep 11, 2006 page 130 of 916
REJ09B0332-0500