SH7065 Datasheet, PDF (88/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Instruction
Instruction Code Operation
Execution
States
T Bit
Indicated by
mnemonic.
Indicated in
MSB ←→ LSB
order.
Indicates summary
of operation.
Value when
no wait
states are
inserted^*1
Value of T bit
after
instruction is
executed.
Explanation of
Symbols
OP.Sz SRC, DEST
OP: Operation
code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination
register
imm: Immediate data
disp: Displacement^*2
Explanation of
Symbols
Explanation of
Symbols
mmmm: Source
register
→, ←: Transfer
direction
nnnn: Destination
register
(xx): Memory
operand
0000: R0
0001: R1
......
1111: R15
iiii: Immediate
data
dddd: Displacement
M/Q/T: Flag bits in
the SR
&: Logical AND
of each bit
|:
Logical OR
of each bit
^:
Exclusive
logical OR of
each bit
Explanation of
Symbols
—: No change
~: Logical NOT
of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
• When there is conflict between an instruction fetch and a data access
• When the destination register of a load instruction (memory → register) is also used
by the following instruction
2. Scaling (×1, ×2, or ×4) is executed according to the instruction operand size. See the
SH-1/SH-2/SH-DSP Software Manual for details.
Rev. 5.00 Sep 11, 2006 page 66 of 916
REJ09B0332-0500