SH7065 Datasheet, PDF (341/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Bits 4 and 3—Transmit Size 1 and 0 (TS1, TS0): These bits specify the transfer data size.
Bit 4: TS1
0
1
Bit 3: TS0
0
1
0
1
Description
Byte size (8 bits)
Word size (16 bits)
Longword size (32 bits)
(Use prohibited)
(Initial value)
Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request is generated after the
number of data transfers specified in DMATCR, or after all chain transfers are completed.
Bit 2: IE
0
1
Description
Interrupt request not generated after number of transfers specified in DMATCR
(Initial value)
Interrupt request generated after number of transfers specified in DMATCR
Bit 1—Transfer End (TE): This bit is set to 1 on completion of the number of transfers specified
in DMATCR, or on completion of all the chain transfers specified in CHNCNT. The timing of TE
bit setting is specified by bit 16 (TES). If the IE bit is set to 1 at this time, an interrupt request is
generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or
clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1,
data transfer is not enabled even if the DE bit is set to 1.
Bit 1: TE
Description
0
Number of transfers specified in DMATCR not completed
(Initial value)
[Clearing conditions]
• When 0 is written to TE after reading TE = 1
• In a power-on reset, and in standby mode
1
Number of transfers specified in DMATCR completed, or all chain transfers
specified in CHNCNT completed
Note: Not initialized in module standby mode.
Rev. 5.00 Sep 11, 2006 page 319 of 916
REJ09B0332-0500