SH7065 Datasheet, PDF (77/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Instruction Formats
nm type 15
0
xxxx nnnn mmmm xxxx
md type 15
0
xxxx xxxx mmmm dddd
nd4 type 15
0
xxxx xxxx nnnn dddd
nmd type 15
0
xxxx nnnn mmmm dddd
Source
Operand
mmmm: register
direct
mmmm: register
direct
mmmm: post-
increment
register indirect
(multiply and
accumulate
operation)
nnnn: * post-
increment
register indirect
(multiply and
accumulate
operation)
mmmm: post-
increment
register indirect
mmmm: register
direct
mmmm: register
direct
mmmmdddd:
register
indirect with
displacement
R0 (register
direct)
mmmm: register
direct
mmmmdddd:
register
indirect with
displacement
Destination
Operand
nnnn: register
direct
nnnn: register
indirect
MACH, MACL
Sample
Instruction
ADD Rm,Rn
MOV.L Rm,@Rn
MAC.W
@Rm+,@Rn+
nnnn: register MOV.L
direct
@Rm+,Rn
nnnn: pre-
MOV.L
decrement
Rm,@-Rn
register indirect
nnnn: indexed MOV.L
register indirect Rm,@(R0,Rn)
R0 (register
direct)
MOV.B
@(disp,Rm),R0
nnnndddd:
register
indirect with
displacement
nnnndddd:
register
indirect with
displacement
nnnn: register
direct
MOV.B
R0,@(disp,Rn)
MOV.L
Rm,@(disp,Rn)
MOV.L
@(disp,Rm),Rn
Rev. 5.00 Sep 11, 2006 page 55 of 916
REJ09B0332-0500