SH7065 Datasheet, PDF (724/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 18 I/O Ports (I/O)
18.2.3 Port A Data Register L (PADRL)
Bit: 15
14
13
12
11
PA15DR PA14DR PA13DR PA12DR —
Initial value:
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R
10
9
8
— PA9DR PA8DR
0
0
0
R
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
— PA1DR PA0DR
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W
R/W
Port A data register L (PADRL) is a 16-bit readable/writable register that stores port A data. Bits
PA15DR to PA0DR correspond to pins PA15/WRHL/HLBS/TCLKD/TIOC3B to PA0/OE0.
When a pin functions as a general output, if a value is written to PADRL, that value is output
directly from the pin, and if PADRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PADRL is read the pin state, not the register value, is
returned directly. If a value is written to PADRL, although that value is written into PADRL it
does not affect the pin state. Table 18.2 summarizes port A data register read/write operations.
PADRL is initialized by an external power-on reset, but is not initialized by a WDT reset or in
standby mode or sleep mode.
Table 18.2 Port A Data Register (PADR) Read/Write Operations
PAIOR
0
1
Pin Function
General input
Read
Pin state
Other than general
input
General output
Other than general
output
Undefined
PADR value
PADR value
Write
Value is written to PADR, but does not
affect pin state
Value is written to PADR, but does not
affect pin state
Write value is output from pin
Value is written to PADR, but does not
affect pin state
Rev. 5.00 Sep 11, 2006 page 702 of 916
REJ09B0332-0500