SH7065 Datasheet, PDF (89/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Table 2.20 Data Transfer Instructions
Instruction
MOV #imm,Rn
MOV.W @(disp,PC),Rn
MOV.L @(disp,PC),Rn
MOV Rm,Rn
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L Rm,@Rn
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L @Rm,Rn
MOV.B Rm,@-Rn
MOV.W Rm,@-Rn
MOV.L Rm,@-Rn
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
MOV.B R0,@(disp,Rn)
MOV.W R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.B @(disp,Rm),R0
MOV.W @(disp,Rm),R0
MOV.L @(disp,Rm),Rn
MOV.B Rm,@(R0,Rn)
Instruction Code
Operation
Execution
States T Bit
1110nnnniiiiiiii imm → sign extension 1
—
→ Rn
1001nnnndddddddd (disp × 2 + PC) → sign 1
—
extension → Rn
1101nnnndddddddd (disp × 4 + PC) → Rn
1
—
0110nnnnmmmm0011 Rm → Rn
1
—
0010nnnnmmmm0000 Rm → (Rn)
1
—
0010nnnnmmmm0001 Rm → (Rn)
1
—
0010nnnnmmmm0010 Rm → (Rn)
1
—
0110nnnnmmmm0000 (Rm) → sign extension 1
—
→ Rn
0110nnnnmmmm0001 (Rm)→ sign extension 1
—
→ Rn
0110nnnnmmmm0010 (Rm) →Rn
1
—
0010nnnnmmmm0100 Rn – 1 → Rn, Rm → (Rn) 1
—
0010nnnnmmmm0101 Rn – 2 → Rn, Rm → (Rn) 1
—
0010nnnnmmmm0110 Rn – 4 → Rn, Rm → (Rn) 1
—
0110nnnnmmmm0100 (Rm) → sign extension 1
—
→ Rn, Rm + 1→ Rm
0110nnnnmmmm0101 (Rm) → sign extension 1
—
→ Rn, Rm + 2 → Rm
0110nnnnmmmm0110 (Rm) → Rn, Rm + 4 → 1
—
Rm
10000000nnnndddd R0 → (disp + Rn)
1
—
10000001nnnndddd R0 → (disp × 2 + Rn)
1
—
0001nnnnmmmmdddd Rm → (disp × 4 + Rn)
1
—
10000100mmmmdddd (disp + Rm) → sign
1
—
extension → R0
10000101mmmmdddd (disp × 2 + Rm) → sign 1
—
extension → R0
0101nnnnmmmmdddd (disp × 4 + Rm) → Rn
1
—
0000nnnnmmmm0100 Rm → (R0 + Rn)
1
—
Rev. 5.00 Sep 11, 2006 page 67 of 916
REJ09B0332-0500