SH7065 Datasheet, PDF (170/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
MCLKCR5
Bit: 15
—
Initial value:
1
R/W: R
14
13
12
11
—
MCLK MCLK
—
191
190
1
—
—
1
R
R/W
R/W
R
10
9
8
—
MCLK MCLK
181
180
1
—
—
R
R/W
R/W
Bit: 7
—
Initial value:
1
R/W: R
6
5
4
3
—
MCLK MCLK
—
171
170
1
—
—
1
R
R/W
R/W
R
2
1
0
—
MCLK MCLK
161
160
1
—
—
R
R/W
R/W
Bits 15, 11, 7, and 3—Reserved: These bits are always read as 1 and should only be written with
1.
Bits 14, 10, 6, and 2—Reserved (MCLKCK5 only): These bits are always read as 1 and should
only be written with 1.
Other Bits—Module Clock 191 to 000 (MCLK191 to MCLK000): These bits specify the clock
division ratio for the corresponding modules. A clock further divided from the master clock
(CKM) or peripheral clock (CKP) set in the frequency control register (FRQCR) of the clock pulse
generator (CPG) is supplied to the corresponding modules. The initial values depend on the clock
mode. See table 4.18 for the correspondence between the register bits and modules.
• MCLK191 to MCLK160
Bit nn1:
MCLKnn1
0
1
Bit nn0:
MCLKnn0
0
1
0
1
Description
Clock supplied to module is not divided
(Initial value in clock modes 1, 3, 5, 6)
Reserved (Do not set)
Clock supplied to module is further divided by 8
Clock supplied to module is further divided by 64
(Initial value in clock modes 0, 2, 4, 7)
Rev. 5.00 Sep 11, 2006 page 148 of 916
REJ09B0332-0500