SH7065 Datasheet, PDF (382/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
9.4 Example of Use
9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory
In the example considered here, on-chip serial communication interface channel 2 (SCI2) receive
data is transferred to external memory using DMAC channel 3. DMAC settings must be
completed and transfer enabled before inputting a transfer request from the serial communication
interface.
Table 9.10 shows the transfer conditions and register set values in this case.
Table 9.10 Example of Use
Transfer Conditions
Transfer source: RDR0 of on-chip SCI0
Transfer destination: External memory
Number of transfers: 8
Transfer source address: Fixed
Transfer destination address: Incremented
Transfer request source: SCI0 (RX0)
Bus mode: Cycle steal
Transfer unit: Byte
Interrupt requested at end of transfer
Channel priority order: 0 > 1 > 2 > 3
Register
SAR3
DAR3
DMATCR3
CHCR3
DMAOR
Set Value
H'FFFF0546
H'04000000
H'00000008
H'13024045
H'0001
9.5 Usage Notes
1. Only word (16-bit) access can be used on the DMA operation register (DMAOR). Word (16-
bit) or longword (32-bit) access can be used on all other registers.
2. When modifying bits RS0 to RS4 in CHCR0 to CHCR3, first clear the DE bit to 0 (when
modifying CHCR, clear the DE bit to 0 beforehand).
3. The NMIF bit in DMAOR is set when an NMI interrupt is input even if the DMAC is not
operating.
4. When setting standby mode, first clear the DME bit in DMAOR to 0 and wait until the DMAC
has completed processing of all accepted transfer requests.
5. Do not access the DMAC, BSC, or UBC on-chip peripheral modules.
Rev. 5.00 Sep 11, 2006 page 360 of 916
REJ09B0332-0500