SH7065 Datasheet, PDF (80/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Double and Single Data Transfer Instructions
The format of double data transfer instructions is shown in table 2.15, and that of single data
transfer instructions in table 2.16.
Table 2.15 Double Data Transfer Instruction Formats
Type
Mnemonic
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X memory NOPX
1111000
0
0
data
transfer
MOVX.W @Ax,Dx
MOVX.W @Ax+,Dx
Ax Dx
0
00
01
10
MOVX.W @Ax+Ix,Dx
11
MOVX.W Da,@Ax
Da
1
01
MOVX.W Da,@Ax+
10
MOVX.W Da,@Ax+Ix
11
Y memory NOPY
111100
0
0
0
data
transfer
MOVY.W @Ay,Dy
MOVY.W @Ay+,Dy
Ay Dy
0
00
01
10
MOVY.W @Ay+Iy,Dy
11
MOVY.W Da,@Ay
Da
1
01
MOVY.W Da,@Ay+
10
MOVY.W Da,@Ay+Iy
11
Legend:
Ax: 0 = R4, 1 = R5
Ay: 0 = R6, 1 = R7
Dx: 0 = X0, 1 = X1
Dy: 0 = Y0, 1 = Y1
Da: 0 = A0, 1 = A1
Rev. 5.00 Sep 11, 2006 page 58 of 916
REJ09B0332-0500