SH7065 Datasheet, PDF (165/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
Register Configuration
Table 4.13 shows the registers used for power-down mode control.
Table 4.13 Power-Down Mode Registers
Name
Abbreviation R/W
Standby control
SBYCR
R/W
register
Module stop control MSTPCR1
R/W
register 1
Module stop control MSTPCR2
R/W
register 2
Module clock control MCLKCR1
R/W
register 1
Module clock control MCLKCR2
R/W
register 2
Module clock control MCLKCR3
R/W
register 3
Module clock control MCLKCR4
R/W
register 4
Module clock control MCLKCR5
R/W
register 5
Initial Value
H'1F
Address
H'FFFF 1004
Access
Size
8, 16, 32
H'0000
H'FFFF 1030 8, 16, 32
H'0000
H'FFFF 1032 8, 16, 32
H'8888 (clock modes 1, 3, 5, 6) H'FFFF 1034
H'FFFF (clock modes 0, 2, 4, 7)
H'8888 (clock modes 1, 3, 5, 6) H'FFFF 1036
H'FFFF (clock modes 0, 2, 4, 7)
H'8888 (clock modes 1, 3, 5, 6) H'FFFF 1038
H'FFFF (clock modes 0, 2, 4, 7)
H'8888 (clock modes 1, 3, 5, 6) H'FFFF 103A
H'FFFF (clock modes 0, 2, 4, 7)
H'CCCC (clock modes 1, 3, 5, 6) H'FFFF 103C
H'FFFF (clock modes 0, 2, 4, 7)
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
4.8.2 Pin Configuration
Table 4.14 shows the pin used for power-down mode control.
Table 4.14 Power-Down Mode Pin
Pin Name
Hardware standby pin
Abbreviation
HSTBY
I/O
Input
Function
Low-level input to this pin places the
chip in the hardware standby state.
Rev. 5.00 Sep 11, 2006 page 143 of 916
REJ09B0332-0500