SH7065 Datasheet, PDF (490/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
11.3.2 Overview of Operation
Count Operation
Set 2Td (Td: value set in TDDR) as the initial value of the TCNT counter when the setting of the
CST bit in TCNR is 0.
When the CST bit is set to 1, TCNT counts up to {value set in TPBR + 2Td}, and then starts
counting down. When TCNT reaches 2Td, it starts counting up again, and continues in this way.
TCNT is constantly compared with TGRU, TGRV, and TGRW. In addition, it is compared with
TGRUU, TGRVU, TGRWU, and TPDR when counting up, and with TGRUD, TGRVD,
TGRWD, and 2Td when counting down.
TDCNT0 to TDCNT5 are read-only counters. It is not necessary to set their initial values.
TDCNT0, TDCNT2, and TDCNT4 start counting up at the falling edge of positive phase compare
match output when TCNT is counting up, and when they match TDDR they are cleared to 0 and
halt.
TDCNT1, TDCNT3, and TDCNT5 start counting up at the falling edge of negative phase compare
match output when TCNT is counting up, and when they match TDDR they are cleared to 0 and
halt.
TDCNT0 to TDCNT5 are compared with TDDR only while a count operation is in progress. No
count operation is performed when the TDDR value is 0.
Figure 11.3 shows an example of the TCNT count operation.
Rev. 5.00 Sep 11, 2006 page 468 of 916
REJ09B0332-0500