SH7065 Datasheet, PDF (758/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
Bit 6—Software Write Enable (SWE): Enables or disables the flash memory. This bit should be
set when setting bits 5 to 0, EBR1 bits 7 to 0, and EBR2 bits 3 to 0.
When SWE = 1, flash memory can only be read in program-verify or erase-verify mode.
Bit 6: SWE
0
1
Description
Programming/erasing disabled
Programming/erasing enabled
[Setting condition]
When FWE = 1
(Initial value)
Bit 5—Erase Setup (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU,
EV, PV, E, or P bit at the same time.
Bit 5: ESU
0
1
Description
Erase setup cleared
Erase setup
[Setting condition]
When FWE = 1 and SWE = 1
(Initial value)
Bit 4—Program Setup (PSU): Prepares for a transition to program mode. Do not set the SWE,
ESU, EV, PV, E, or P bit at the same time.
Bit 4: PSU
0
1
Description
Program setup cleared
Program setup
[Setting condition]
When FWE = 1 and SWE = 1
(Initial value)
Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE,
ESU, PSU, PV, E, or P bit at the same time.
Bit 3: EV
0
1
Description
Erase-verify mode cleared
Transition to erase-verify mode
[Setting condition]
When FWE = 1 and SWE = 1
(Initial value)
Rev. 5.00 Sep 11, 2006 page 736 of 916
REJ09B0332-0500